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rev. prh information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. software selectable true bipolar input, 2-channel, 12-bit plus sign adc preliminary technical data AD7322* features ? 12-bit plus sign sar adc ? true bipolar analog inputs ? software selectable input ranges 10v, 5v, 2.5v, 0 to 10v ? two analog inputs with channel sequencer ? single ended, true differential and pseudo differential capability. ? high analog input impedance ? low power:- 26 mw max at 1 msps ? full power signal bandwidth: >7 mhz ? internal 2.5 v reference ? high speed serial interface ? power down modes ? 14-lead tssop ? i cmos tm process technology ? for 8 and 4 channel equivalent devices see ad7328 and ad7324 respectively. general description the AD7322 is a 2-channel, 12-bit plus sign successive approximation adc. the adc has a high speed serial interface that can operate at throughput rates up to 1 msps. the AD7322 can accept true bipolar analog input signals. the AD7322 has four software selectable inputs ranges, 10v, 5v, 2.5v and 0 to 10v. each analog input channel can be independently programmed to one of the four input ranges. the analog input channels on the AD7322 can be programmed to be single-ended, true differential or pseudo differential. the AD7322 contains a 2.5v internal reference. the AD7322 also allows for external reference operation. if a 3v reference is applied the ref in/out pin the AD7322 can accept a true bipolar 12v analog input. minimum v dd and v ss supplies of 12v are required for the 12v input range. * protected by u.s. patent no. 6,731,232 functional block diagram figure 1. product highlights 1. the AD7322 can accept true bipolar analog input signals, 10v, 5v, 2.5v and 0 to 10v unipolar signals. 2. the two analog inputs can be configured as two single- ended inputs, one true differential or one pseudo differential input. the AD7322 has high impedance analog inputs. 3. the AD7322 features a high speed serial interface. throughput rates up to 1 msps can be achieved on the AD7322. 4. low power, 26 mw at maximum throughput rate of 1 msps. device number number of bits number of channels ad7328 12-bits plus sign 8 ad7324 12-bits plus sign 4 i cmos tm process technology for analog systems designers within industrial/instrumentation eq uipment oems who need high performance ics at higher-voltage l evels, i cmos is a technology platform that enables the development of analog ics capable of 30v and operating at +/- 15v supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance.
AD7322 preliminary technical data rev. prh | page 2 of 18 table of contents AD7322?specifications.................................................................. 3 absolute maximum ratings............................................................ 6 pin functional descriptions ....................................................... 7 terminology ...................................................................................... 8 theory of operation.....................................................................9 AD7322 registers ........................................................................... 12 serial interface ................................................................................ 17 outline dimensions .................................................................. 18 revision history revision prh: preliminary version
AD7322 preliminary technical data rev. prh | page 3 of 18 AD7322?specifications 1 table 1. unless otherwise noted, v dd = + 12v to +16.5v, v ss = -12v to C16.5v, v cc = 2.7v to 5.25v, v drive = 2.7v to 5.25v, v ref = 2.5v internal/external, f sclk = 20 mhz, f s = 1 msps t a = t max to t min parameter specification unit s test conditions/comments dnamic performance f in = 50 khz sine wave signal to noise ratio (snr) 2 76 db min differential mode 72 db min single-ended /pseudo differential mode signal to noise + distortion (sinad) 2 75 db min differential mode 71.5 db min single-ended/pseudo differential mode total harmonic distortion (thd) 2 -80 db max peak harmonic or spurious noise (sfdr) 2 -80 db max intermodulation distortion (imd) 2 f a = 40.1 khz, f b = 41.5 khz second order terms -88 db typ third order terms -88 db typ aperature delay 2 10 ns max aperature itter 2 50 ps typ common mode rejection (cmrr) 2 tbd db typ channel-to-channel isolation 2 -80 db typ f in = 400 khz full power bandwidth 2 7 1.5 mhz typ mhz typ 3 db 0.1 db dc accurac resolution 12+sign bits integral nonlinearity 2 1.5 lsb max differential nonlinearity 2 0.95 lsb max guaranteed no missing codes to 13-bits offset error 3 8 lsb max unipolar range with straight binary output coding offset error match 2 0.5 lsb max gain error 2 6 lsb max gain error match 2 0.6 lsb max positive full-scale error 2 3 lsb max bipolar range with twos complement output coding positive full scale error match 2 0.6 lsb max bipolar zero error 2 8 lsb max bipolar zero error match 2 0.5 lsb max negative full scale error 2 4 lsb max negative full scale error match 2 0.5 lsb max analog input input voltage ranges (programmed via range register) 10v 5v 2.5v 0 to 10v volts v dd = +10v min , v ss = -10v min, v cc = 2.7v to 5.25v v dd = +5v min, v ss = -5v min, v cc = 2.7v to 5.25v v dd = +5v min, v ss = - 5v min, v cc = 2.7v to 5.25v v dd = +10v min, v ss = 0 v min, v cc = 2.7v to 5.25v see table 5 dc leakage current 10 na max input capacitance 12 pf typ wh en in track, 10v range 15 pf typ when in track, 5v, 0 to 10v range 20 pf typ when in track, 2.5v range 3 pf typ when in hold reference input/output input voltage range +2.5 to +3v v min to max input dc leakage current 1 a max input capactiance 20 pf typ reference output voltage 2.49/2.51 vmin/max reference temperature coefficient 25 ppm/cmax 10 ppm/ctyp
AD7322 preliminary technical data rev. prh | page 4 of 18 parameter specification unit s test conditions/comments reference output impedance 25 : typ logic inputs input high voltage, v inh 2.4 v min input high voltage, v inl 0.8 v max v cc = 4.75 to 5.25 v o.4 v max v cc = 2.7 to 3.6 v input current, i in 1 a max v in = 0v or v cc input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v drive - 0.2v v min i source = 200 a output low voltage, v ol 0.4 v max i sink = 200 a floating state leakage current 1 a max floating state output capacitance 3 10 pf max output coding straight natural binary coding bit set to 1 in control register two?s complement coding bit set to 0 in control register conversion rate conversion time 800 ns max 16 sclk cycles with sclk = 20 mhz track-and-hold acquisition time 200 ns max sine wave input 200 ns max full scale step input throughput rate 1 msps max see serial interface section power requirements digital inputs = 0v or v cc v dd 4 12v/+16.5v v min/max see table 5 v ss 4 -12v/16.5v v min/max see table 5 v cc 2.7v / 5.25v v min/max see table 5 v drive 2.7v/5.25v v min/max normal mode i dd 300 a max v dd = +16.5v i ss 370 a max v ss = -16.5v i cc 2 ma max v cc = 5.25v auto-standby mode f sample = tbd i dd tbd a max i ss tbd a max i cc 1.6 ma typ auto-standby mode f sample = tbd i dd tbd a max i ss tbd a max i cc 1 ma typ full shutdown mode i dd 0.9 a max i ss 0.9 a max i cc 0.9 a max sclk on or off power dissipation normal mode 26 mw max v dd = +16.5v, v ss = -16.5v, v cc = 5.25v, full shutdown mode 35 w max v dd = +16.5v, v ss = -16.5v, v cc = 5.25v, notes 1 temperature ranges as follows: -40c to +85c 2 see terminology 3 guaranteed by characterization 4 functional from v dd = +4.75v and v ss = -4.75v. specifications subject to change without notice.
AD7322 preliminary technical data rev. prh | page 5 of 18 timing specifications table 2. unless otherwise noted, v dd = +12v to + 16.5v, v ss = -12v to C16.5v, v cc =2.7v to 5.25, v drive =2.7v to 5.25, v ref = 2.5v internal/external, t a = t max to t min parameter limit at t min , t max unit description f sclk 10 khz min 20 mhz max t convert 16t sclk ns max t sclk = 1/f sclk t uiet 50 ns max minimum time between end of serial read and next falling edge of cs t 1 10 ns min minimum cs pulse width t 2 10 ns min cs to sclk setup time t 3 20 ns max delay from cs until d out three-state disabled t 4 tbd ns max data access time after sclk falling edge. t 5 0.4t sclk ns min sclk low pulsewidth t 6 0.4t sclk ns min sclk high pulsewidth t 7 10 ns min sclk to data valid hold time t 8 25 ns max sclk falling edge to d out high impedance 10 ns min sclk falling edge to d out high impedance t 9 tbd ns min din set-up time prior to sclk falling edge t 10 5 ns min din hold time after sclk falling edge 1 s max power up from auto standby tbd s max power up from full shutdown/auto shutdown mode figure 2. serial interface timing diagram
AD7322 preliminary technical data rev. prh | page 6 of 18 absolute maximum ratings table 3. t a = 25c, unless otherwise noted v dd to agnd, dgnd -0.3 v to +16.5 v v ss to agnd, dgnd +0.3 v to C16.5 v v cc to agnd, dgnd -0.3v to +7v v drive to v cc -0.3 v to v cc + 0.3v agnd to dgnd -0.3 v to +0.3 v analog input voltage to agnd v ss -0.5v to v dd + 0.5v digital input voltage to dgnd -0.3 v to +7 v digital output voltage to gnd -0.3 v to v drive +0.3v ref in to agnd -0.3 v to v cc +0.3v input current to any pin except supplies 2 10ma operating temperature range -40c to +85c storage temperature range -65c to +150c unction temperature +150c tssop package a thermal impedance 143 c/w c thermal impedance 45 c/w pb-free temperature, soldering reflow 260(+0)c esd tbd
AD7322 preliminary technical data rev. prh | page 7 of 18 pin functional descriptions 14 13 12 11 9 top view (not to scale) 8 1 2 3 4 7 6 5 AD7322 din sclk refin/out v ss dgnd dout v in 1 10 v drive v in 0 agnd dgnd v dd figure 3. AD7322 pin configuration tssop table 4. AD7322 pin function descriptions pin mnemonic pin number description sclk 14 serial clock. logic input. a se rial clock input provides the sc lk used for accessing the data from the AD7322. this clock is also used as the clock source for the conversion process. d out 12 serial data output. the conversi on output data is suppl ied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input and 16 sclks are required to access the data. the data stream consists of two leading zeros, one channel identification bit, a sign bit followed by 12 bits of conversion data. the data is provided msb first. see the serial interface section. cs 1 chip select. active low logic input. this inp ut provides the dual function of initiating conversions on the AD7322 and frames the serial data transfer. din 2 data in. data to be written to the on-chip register s is provided on this in put and is clocked into the register on the falling edge of sclk. see register section. agnd 4 analog ground. ground reference point for all an alog circuitry on the AD7322. all analog input signals and any external reference signal sh ould be referred to this agnd voltage. ref in/ ref out 5 reference input/ reference output pin. when en abled the on-chip reference is available on this pin for use external to th e AD7322. alternativley, the inte rnal reference can be disabled and an external reference appl ied to this input. when usin g the AD7322 with an external reference, the internal reference must be di sabled via the control register. the nominal reference voltage is 2.5 v, which appears at the pin. the default on power up is for external reference operation. a 470 nf decoupling capacitor sgould be placed on the reference pin. v cc 10 analog supply voltage, 2.7 v to 5.25 v. this is the supply voltage for the adc core on the AD7322. this supply should be decoupled to agnd. v dd 9 positive power supply voltage. this is the posi tive supply voltage for the analog input section. v ss 6 negative power supply voltage. this is the ne gavtive supply voltage for the analog input section. dgnd 3,13 this is the digital ground pin. v drive 11 logic power supply input. the voltage applied to this pin determines the operating voltge of the sertial inteface. vin0-vin1 7,8 analog input 0 through analog input 1. the an alog inputs are multiplexed into the on-chip track-and-hold. the analog input channel for conversion is selected by programming the channel address bit add0, in the control register . the inputs can be configured as 2 single- ended inputs, 1 true differential input pair, 1 pseudo differential inputs. the configuration of the analog inputs is selected by programmin g the mode bits, mode1 and mode0, in the control register. the input range on each in put channel is controlled by programming the range register. inputs ranges of 10v, 5v, 2.5 v and 0 to 10v can be selected on each analog input channel. see register section.
AD7322 preliminary technical data rev. prh | page 8 of 18 terminology differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. offset code error this applies to straight binary output coding. it is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., agnd + 1 lsb. offset error match this is the difference in offset error between any two input channels. gain error this applies to straight binary output coding. it is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., 4 x vref C 1 lsb, 2 x v ref C1 lsb, v ref C1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two input channels channels. bipolar zero code error this applies when using twos complement output coding and a bipolar analog input. it is the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, i.e., agnd - 1 lsb. bipolar zero code error match this refers to the difference in bipolar zero code error between any two input channels. positive full scale error this applies when using twos complement output coding and any of the bipolar analog input ranges. it is the deviation of the last code transition (011110) to (011111) from the ideal ( +4 x v ref - 1 lsb, + 2 x v ref C 1 lsb, + v ref C 1 lsb) after the bipolar zero code error has been adjusted out. positive full scale error match this is the difference in positive full scale error between any two input channels. negative full scale error this applies when using twos complement output coding and any of the bipolar analog input ranges. this is the deviation of the first code transition (10000) to (10001) from the ideal (i.e., - 4 x v ref + 1 lsb, - 2 x v ref + 1 lsb, - v ref + 1 lsb) after the bipolar zero code error has been adjusted out. negative full scale error match this is the difference in negative full scale error between any two input channels. track-and-hold acquisition time the track-and-hold amplifier returns into track mode after the fifteenth sclk falling edge. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all non-fundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal to (noise + distortion) = (6.02n + 1.76) db s or a 1it onerter tis is 0.02 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the AD7322 it is defined as 1 2 6 2 5 2 4 2 3 2 2 log 20 ) ( v v v v v v db thd where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full-scale, 400 khz sine wave signal to all unselected input channels and determining how much that signal is attenuated in
preliminary technical data AD7322 rev. prh| page 9 of 18 the selected channel with a 50 khz signal. the figure given is the worst-case across all eight channels for the AD7322. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with non-linearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the AD7322 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. psr (power supply rejection) variations in power supply will affect the full-scale transition but not the converters linearity. power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. see typical performance curves. theory of operation circuit information the AD7322 is a fast, 2-channel, 12-bit plus sign, bipolar input, serial a/d converter. the AD7322 can accept bipolar input ranges that include 10v, 5v, 2.5v, it can also accept 0 to 10v unipolar input range. a different analog input range can be programmed on each analog input channel via the on-chip range register. the AD7322 has a high speed serial interface that can operate at throughput rates up to 1 msps. the AD7322 requires v dd and v ss dual supplies for the high voltage analog input structure. these supplies must be equal to or greater than the analog input range. see table 5 for the minimum requirements on these supplies for each analog input range. the AD7322 requires a low voltage 2.7v to 5.25 v v cc supply to power the adc core. table 5. reference and supply requirements for each analog input range selected analog input range (v) reference voltage (v) full scale input range(v) av cc (v) minimum v dd /v ss (v) 2.5 10 3/5 10 10 3.0 12 3/5 12 2.5 5 3/5 5 5 3.0 6 3/5 6 2.5 2.5 3/5 5 2.5 3.0 3 3/5 5 2.5 0 to 10 3/5 +10/agnd 0 to 10 3.0 0 to 12 3/5 +12/agnd in order to meet the specified performance specifications when the AD7322 is configured with the minimum v dd and v ss supplies for a chosen analog input range the throughput rate should be decreased from the maximum throughput range. see typical performance curves. the analog inputs can be configured as either 2 single-ended inputs, 1 true differential inputs, or 1 pseudo differential input. selection can be made by programming the mode bits, mode0 and mode1, in the on-chip control register. the serial clock input accesses data from the part but also provides the clock source for each successive approximation adc. the AD7322 has an on-chip 2.5 v reference. if an external reference is the preferred option the user must write to the reference bit in the control register to disable the internal reference. the AD7322 also features power-down options to allow power saving between conversions. the power-down modes are selected by programming the power management bits in the on- chip control register, as described in the modes of operation section. converter operation the AD7322 is a successive approximation analog-to-digital converter, based around two capacitive dacs. figure 4 and figure 5 show simplified schema tics of the adcs in single ended mode during the acquisition and conversion phase, respectively. figure 6 and figure 7 show simplified schematics of the adc in differential mode during acquisition and conversion phase, respectively. the adc is comprised of control logic, a sar, and a capacitive dac. in figure 4 (the acquisition phase), sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal on the input.
AD7322 preliminary technical data rev. prh | page 10 of 18

figure 4. adc acquisition phase(single ended) when the adc starts a conversion (figure 5), sw2 will open and sw1 will move to position b, causing the comparator to become unbalanced. the control logic and the charge redistribution dac is used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code.

figure 5. adc conversion phase(single ended) figure 6 shows the differential configuration during the acquisition phase. for the conversion phase, sw3 will open, sw1 and sw2 will move to position b, see figure 7. the output impedances of the source driving the vin+ and vin- pins must be matched; otherwise the two inputs will have different settling times, resulting in errors.

figure 6. adc differential config uration during acquisition phase

figure 7. adc differential config uration during conversion phase output coding the AD7322 default output coding is set to twos complement. the output coding is controlled by the coding bit in the control register. to change the output coding to straight binary coding the coding bit in the control register must be set. when operating in sequence mode the output coding for each channel in the sequence will be the value written to the coding bit during the last write to the control register. transfer functions the designed code transitions occur at successive integer lsb values (i.e., 1 lsb, 2 lsb, and so on). the lsb size is dependant on the analog input range selected. table 6. lsb sizes for each analog input range input range full scale range/8192 lsb size 10v 20v/8192 2.441 mv 5v 10v/8192 1.22 mv 2.5v 5v/8192 0.61 mv 0 to 10v 10v/8192 1.22 mv the ideal transfer characteristic for the AD7322 when twos complement coding is selected is shown in figure 8, and the ideal transfer characteristic for the AD7322 when straight binary coding is selected is shown in figure 9. 000...000 - fsr/2 + 1lsb adc code analog input 011...111 100...001 100...010 011...110 000...001 111...111 +fsr/2 - 1lsb 100...000 v ref - 1lsb figure 8. twos complement transfer characteristic (bipolar ranges) 000...000 -fsr/2 adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 1lsb fsr/2 -1lsb figure 9. straight binary transfer characteristic (bipolar ranges) analog input the analog inputs of the AD7322 may be configured as single- ended, true differential or pseudo differential via the control register mode bits as shown in table 9 of the register section. the AD7322 can accept true bipolar input signals. on power up the analog inputs will operate as 2 single-ended analog input channels. if true differential or pseudo differential is
preliminary technical data AD7322 rev. prh| page 11 of 18 required, a write to the control register is necessary to change this configuration after power up. figure 10 shows the equivalent analog input circuit of the AD7322 in single-ended mode. figure 11 shows the equivalent analog input structure in differential mode. the two diodes provide esd protection for the analog inputs. d d v dd c2 r1 vin0 v ss c1 figure 10. equivalent analog input circuit-(single ended) d d v dd c2 r1 vin+ v ss c1 d d v dd c2 r1 vin- v ss c1 figure 11. equivalent analog input circuit-(differential) care should be taken to ensure the analog input never exceeds the v dd and v ss supply rails by more than 300 mv. this will cause the diodes to become forward biased and start conducting into either the v dd or v ss rails. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the capacitor c1, in figure 10 and figure 11 is typically 4 pf and can primarily be attributed to pin capacitance. the resistor r1, is a lumped component made up of the on-resistance of the input multiplexer and the track-and-hold switch. the capacitor c2, is the sampling capacitor, its capacitance will vary depending on the analog input range selected. track-and-hold section the track-and-hold on the analog input of the AD7322 allows the adc to accurately convert an input sine wave of full scale amplitude to 13-bit accuracy. the input bandwidth of the track-and-hold is greater than the nyquist rate of the adc , the AD7322 can handle frequencies up to 7 mhz. the track-and-hold enters its tracking mode on the 15 th sclk falling edge after the cs falling edge. the time required to acquire an input signal will depend on how quickly the sampling capacitor is charged. with zero source impedance 200 ns will be sufficient to acquire the signal to the 13-bit level. the acquisition time required is calculated using the following formula t ac = 10 x ((r source + r) c) where c is the sampling capacitance and r is the resistance seen by the track-and-hold amplifier looking back on the input. for the AD7322, the value of r will include the on-resistance of the input multiplexer. the value of r is typically 300 . r source should include any extra source impedance on the analog input. tpical connection diagram figure 12 shows a typical connection diagram for the AD7322. in this configuration the agnd pin is connected to the analog ground plane of the system. the dgnd pin is connected to the digital ground plane of the system. the analog inputs on the AD7322 can be configured to operate in single ended, true differential or pseudo differential mode. the AD7322 can operate with either the internal or an external reference. in figure 12, the AD7322 is configured to operate with the internal 2.5v reference. a 470 nf decoupling capacitor is required when operating with the internal reference. the v cc pin can be connected to either a 3v or a 5v supply voltage. the v dd and v ss are the dual supplies for the high voltage analog input structures. the voltage on these pins must be equal to or greater than the highest analog input range selected on the analog input channels, see table 5 for more information. the v drive pin is connected to the supply voltage of the microprocessor. the voltage applied to the v drive input controls the voltage at which the serial interface operates. figure 12. typical connection diagram
AD7322 preliminary technical data rev. prh | page 12 of 18 AD7322 registers the AD7322 has two-programmable registers, the control register and the range register . these registers are write only registers. addressing these registers a serial transfer on the AD7322 consists of 16 sclk cycles. the three msbs on the din line during each 16 sclk transfer are dec oded to determine which register is addressed. the three msbs consists of the write bit, zero bit and a register select bit. the regist er select bit is used to determine which of the two on-board registers is selected. the write bit will determine if the data on the din line following the register select bit is loaded into the addressed register or not. if the write bit is 1 the bits will be loaded into the r egister addressed by the register select bit. if the write bit is a 0 the data on the din will not be loaded into any register and both registers wi ll remain unchanged. table 7. decoding register select bit and write bit. write zero register select comment 0 0 0 data on the din line during this serial transfer will be ignored. register contents will remain unchanged. 1 0 0 this combination selects the control register . the subsequent 12 bits will be loaded into the control register. 1 0 1 this combination selects the range register. the subsequent 8 bits will be loaded into the range register. control register the control register is used to select the analog input configur ation, reference, coding, power mode etc. the control register is a write only 12-bit register. data loaded on the din line corresponds to the AD7322 configuration for the next conversion. data should be loaded into the control register after the range register has been initialized. the bit functions of the control register are o utlined in table 8. control register (the power-up status of all bits is 0) table 8. control register msb lsb write zero register select zero zero add0 mode1 mode0 pm1 pm0 coding ref seq1 seq2 zero 0 bit mnemonic comment 10 add0 this channel address bit is used to select the analog in put channel for the next conversion if the sequencer is not being used. 9, 8 mode1, mode0 these two mode bits are used to se lect the configuation on the two an alog input pins. they are used in conjunction with the channel address bit. on the AD7322 the analog inputs can be configured as either 2 single ended inputs, 1 fully differential inp ut, 1 pseudo differential input. see table 9. 7,6 pm1, pm0 power management bits. these two bits are used to se lect different power mode options on the AD7322. see table 10. 5 coding this bit is used to select the type of output coding the AD7322 will use for the next conversion result. if the coding = 0 then the output coding wi ll be 2s complement. if coding = 1, then the output coding will be straight binary. when operating in sequence mode th e output coding for each channel will be the value written to the coding bit during the last write to the control register. 4 ref reference bit. this bit is used to en able or disable the internal reference. if this ref = 0 then the external reference will be enabled and used for the next conversion and the internal reference will be disabled. if ref = 1 then the internal reference will be used for the ne xt conversion. when operating in sequence mode the
preliminary technical data AD7322 rev. prh| page 13 of 18 reference used for each channel will be the value writte n to the ref bit during the last write to the control register. 3,2 seq1/seq2 the sequence 1 and sequence 2 bits are used to control the operation of the sequencer. see table 11 14,12,11,1 zero a zero must be written to this bit to ensure correct operation of the AD7322. table 9. analog input configuration selection table 10. power mode selection table 11. sequencer selection channel address bit mode1 =1, mode0 = 1 mode1 = 1, mode0 =0 mode1 = 0, mode0 =1 mode1 =0, mode0 =0 1 pseudo differential i/p 1fully differential i/p not allowed two-single ended i/ps add0 vin+ vin- vin+ vin- vin+ vin- 0 vin0 vin1 vin0 vin1 vin0 agnd 1 vin0 vin1 vin0 vin1 vin1 agnd pm1 pm0 description 1 1 full shutdown mode, in this mode all internal circuitry on the AD7322 is powered down. information in the control register is retained when the AD7322 is in full shutdown mode. 1 0 auto shutdown mode, the AD7322 will enter full shut down at the end of each conversion when the control register is updated. all internal circuitry is powered down in full shutdown. 0 1 auto standby mode, in this mode all internal circuitry is powered down excluding the internal reference. the AD7322 will enter auto standby mode at the end of the conversion after the control register is updated. 0 0 normal mode, all internal circuitry is powered up at all times. seq1 seq2 sequence type 0 0 the channel sequencer is not used. the analog ch annel selected by programmi ng the add0 bit in the control register selects the next channel for conversion. 1 0 this configuration is used in conjunction with the ch annel address bit in the cont rol register. provided that the channel address bit is 1, the adc will convert firs tly on channel 0 then chan nel 1 and will repeat this sequence until the seq bits are changed in the control register. 1 1 the channel sequencer is not used. the analog ch annel selected by programmi ng the add0 bit in the control register selects the next channel for conversion.
AD7322 preliminary technical data rev. prh | page 14 of 18 range register the range register to used to select one analog input range per analog input channel. it is a 4-bit write only register, with t wo dedicated range bits for each of the two analog input channels. there are four analog input ranges to choose from, 10v, 5v, 2.5v, 0 to 10v. a write to the range register is selected by setting the write bit to 1 and the register select bit to 1. once the initial write to the range register occurs the AD7322 automatically configures the two analog inputs to the appropriate range, as indicated by the range r egister, each time any one of these analog input channels is selected. th e 10v input range is selected by default on each analog input channel. see table 12. table 12. range register write zero register select vin0a vin0b vin1a vin1b 0 0 0 0 0 0 0 0 0 vinxa vinxb description 0 0 this combination selects the 10v input range on analog input x. 0 1 this combination selects the 5v input range on analog input x. 1 0 this combination selects the 2.5v input range on analog input x. 1 1 this combination selects the 0 to 10v input range on analog input x.
AD7322 preliminary technical data rev. prh | page 15 of 18 reference the AD7322 can operate with either the internal 2.5v on-chip reference or an externally applied reference. the internal reference is selected by setting the ref bit in the control register to 1. on power up the ref bit will be 0, selecting the external reference for the AD7322 conversion. for external reference operation the ref in /ref out pin should be decoupled to agnd with a 470 nf capacitor. the internal reference circuitry consists of a 2.5v band gap reference and a reference buffer. when operating the AD7322 in internal reference mode the 2.5v internal reference is available at the ref in /ref out pin. when using the AD7322 with the internal reference the refin/refout pin should be decoupled to agnd using a 470 nf cap. it is recommended that the internal reference be buffered before applying it else where in the system. the AD7322 is specified for a 2.5v to 3v reference range. when a 3v reference is selected the ranges will be, 12v, 6v, 3v and 0 to 12v. for these ranges the v dd and v ss supply must be equal to or greater than the max analog input range selected. on power up if the internal reference operation is required for the adc conversion, a write to the control register is necessary to set the ref bit to 1. during the control register write the conversion result from the first initial conversion will be invalid. the reference buffer will require tbd us to power up and charge the 470 nf decoupling cap, during the power up time the conversion result from the adc will be invalid.
AD7322 preliminary technical data rev. prh | page 16 of 18 modes of operation the AD7322 has a number of different modes of operation. these modes are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for the differing application requirements. the mode of operation of the AD7322 is controlled by the power management bits, pm1 and pm0, in the control register as detailed in table 10 .the default mode is normal mode, where all internal circuitry is fully powered up. normal mode (pm1 = pm0 = 0) this mode is intended for the fastest throughput rate performance, the AD7322 is fully powered up at all times. figure 13 shows the general diagram of operation of the AD7322 in normal mode. the conversion is initiated on the falling edge of cs and the track and hold will enter hold mode as described in the serial interface section. the data on the din line during the 16 sclk transfer will be loaded into one of the on-chip registers, provided the write bit is set. the register is selected by programming the register select bits, see table 1 of the register section. figure 13. normal mode e d722 ill reain ll oered at te end o te onersion roided ot 1 and 0 ontain 0 in te ontrol egister. siteen serial lo les are reired to olete te onersion and aess te onersion reslt. t te end o te onersion s a idle ig ntil te net onersion or a idle lo ntil soetie rior to te net onersion. ne te data transer is olete anoter onersion an e initiated ater te iet tie t as elased. full shutdown mode (pm1 = pm0 = 1) in this mode all internal circuitry on the AD7322 is powered down. the part retains information in the registers during full shut down. the AD7322 remains in full shutdown mode until the power managements bits in the control register, pm1 and pm0, are changed. if a write to the control register occurs while the part is in full shut down mode, with the power management bits, pm1 and pm0 set to 0, normal mode, the part will begin to power up on the cs rising edge. to ensure the AD7322 is fully powered up, t power up , should elapse before the next cs falling edge. auto shutdown mode (pm1 = 1, pm0 = 0) once the auto shutdown mode is selected the AD7322 will automatically enter shutdown at the end of each conversion. the AD7322 retains information in the registers during shutdown. the track-and-hold is in hold during shutdown. on the falling cs edge, the track-and-hold that was in hold during shutdown will return to track. the power-up from auto shutdown is tbd s in this mode the power consumption of the AD7322 is greatly reduced with the part entering shutdown at the end of each conversion. when the control registers is programmed to move into auto shutdown mode, it does so at the end of the conversion. auto standby mode (pm1 = 0, pm0 =1) in auto standby mode portions of the AD7322 are powered down but the on-chip reference remains powered up. the reference bit in the control register should be 0 to ensure the on-chip reference is enabled. this mode is similar to auto shutdown but allows the AD7322 to power up much faster, allowing faster throughput rates to be achieved. the AD7322 will enter standby at the end of the conversion. the part retains information in the registers during standby. the AD7322 will remain in standby until it receives a cs falling edge. the adc will begin to power up on the cs falling edge. on this cs falling edge the track-and-hold that was in hold mode while the part was in standby will return to track. wake- up time from standby is 1 s. the user should ensure that 1 s has elapsed before attempting a valid conversion. when running the AD7322 with the maximum 20 mhz sclk, one dummy conversion of 16 x sclks is sufficient to power up the adc. this dummy conversion effectively halves the throughput rate of the AD7322, with every second conversion result being a valid result. once auto standby mode is selected, the adc can move in and out of the low power state by controlling the cs signal.
AD7322 preliminary technical data rev. prh | page 17 of 18 serial interface figure 14 shows the timing diagram for the serial interface of the AD7322. the serial clock applied to the sclk pin provides the conversion clock and also controls the transfer of information to and from the AD7322 during a conversion. the cs signal initiates the data transfer and the conversion process. the falling edge of cs puts the track-and-hold into hold mode, take the bus out of three-state and the analog input signal is sampled at this point. once the conversion is initiated it will require 16 sclk cycles to complete. the track-and-hold will go back into track on the 15th sclk falling edge. on the sixteenth sc lk falling edge, the dout line will return to three-state. if the rising edge of cs occurs before 16 sclk cycles have elapsed, the conversion will be terminated, the dout line will return to three-state, and depending on when the cs signal is brought high the addressed register may or may not be updated. data is clocked into the AD7322 on the sclk falling edge. the three msb on the din line are decoded to select which register is being addressed. the control register is an eleven bit register, if the control register is addressed by the three msb, the data on the din line will be loaded into the control on the 15 th sclk falling edge. if the range registers is addressed the data on the din line will be loaded into the addressed register on the 11 th sclk falling edge. conversion data is clocked out of the AD7322 on each sclk falling edge. data on the dout line will consist of two leading zeros, a channel identifier bit, a sign bit and the 12-bit conversion result. the channel identifier bit is used to indicate which channel the conversion result corresponds to. figure 14. serial interface timing diagram (control register write)
AD7322 preliminary technical data rev. prh | page 18 of 18 outline dimensions 14-lead thin shrink small outline (tssop) (ru-14) ordering guide AD7322 products temperature package package description package outline AD7322bruz ?40c to +85c tssop ru-14 eval-AD7322cb 1 evaluation board eval-control brd2 2 controller board notes 1 this can be used as a stand-alone evaluation board or in conjunction with the eval-control board for evaluation/demonstration purposes. 2 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in th e cb designators. to order a complete evaluation kit, the particular adc evaluation board, e .g., eval-AD7322cb, the eval-control b rd2, and a 12v transformer must be ordered. see relevant evaluation board technical note fo r more information. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.

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